`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   20:13:05 01/26/2013
// Design Name:   ppunit
// Module Name:   E:/ParaCPU/shaoxia-project/hdl/src/tb_modules/tb_ppunit.v
// Project Name:  ise_ParaCPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: ppunit
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
`define MEM_DEPTH 4096
module tb_ppunit;

	// Inputs
	reg clk;
	reg rst_n;
	reg [31:0] instr;
	reg [31:2] instr_addr;
	reg [127:0] data;
	reg [31:4] data_addr;
	reg wr_data_consumed;

	// Outputs
	wire [31:2] instr_req_addr;
	wire instr_req;
	wire [31:2] data_req_addr;
	wire data_req;
	wire [31:0] wr_data;
	wire [31:2] wr_data_addr;
	wire wr_data_en;
	wire busy;

	reg [31:0] mem [`MEM_DEPTH-1:0];
	// Instantiate the Unit Under Test (UUT)
	integer i;
	ppunit #(.PPID(32'h3))uut (
		.clk(clk), 
		.rst_n(rst_n), 
		.instr(instr), 
		.instr_addr(instr_addr), 
		.instr_req_addr(instr_req_addr), 
		.instr_req(instr_req), 
		.data(data), 
		.data_addr(data_addr), 
		.data_req_addr(data_req_addr), 
		.data_req(data_req), 
		.wr_data(wr_data), 
		.wr_data_addr(wr_data_addr), 
		.wr_data_en(wr_data_en), 
		.wr_data_consumed(wr_data_consumed), 
		.busy(busy)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		rst_n = 0;
		instr = 0;
		instr_addr = 0;
		data = 0;
		data_addr = 0;
		wr_data_consumed = 0;
		for(i=0;i<`MEM_DEPTH;i=i+1)
			mem[i]=0;
		// Wait 100 ns for global reset to finish
		#100 rst_n=1; 
        
		// Add stimulus here

	end
	
	always @ (posedge clk)
	begin
		getInstr_TEST1(instr_req_addr);
	end
	
	always @ (posedge clk)
	begin
		if(wr_data_en)
		begin
			mem[wr_data_addr]<=wr_data;
			wr_data_consumed<=1;
		end
		else
		begin
			wr_data_consumed<=0;
		end
	end
	//read mem
	always @ (posedge clk)
	begin
		data<=mem[data_req_addr[31:2]];
		data_addr<=data_req_addr;
	end
	always #1 clk=~clk;
task getInstr_TEST1;
input [31:2] addr;
begin
	//always @ (posedge clk)
	//	#0.1	
	case(addr)
	32'h0:
		begin
		instr=32'h01000001;//start pp ppcode
		instr_addr=addr;		
		end
	32'h1:
		begin
		instr=32'ha001000a;//ppcode:@irmov16,10,r1
		instr_addr=addr;
		end
	32'h2:
		begin
		instr=32'hb0101000;//@add r1,r0,r1
		instr_addr=addr;
		end
	32'h3:
		begin
		instr=32'h80000000;//@halt
		instr_addr=addr;
		end
	endcase
	//default case is no maintain the previos values.
end
endtask  
endmodule

